1. Field of the Invention
The invention relates to a method and apparatus of interfacing a direct memory access (DMA) controller to a non-ISA bus and more particularly to utilizing a personal computer (PC) compatible DMA controller in a distributed DMA architecture on non-ISA buses, especially the PCI bus.
2. Description of the Related Art
Personal computers are constantly changing as new technologies evolve and are incorporated into the computer. Performance improvements in microprocessors and memory have resulted in computers so powerful that they can perform tasks that before could only be performed by large mainframe computers. However, to fully replace a mainframe computer, the computer must have significant memory and storage capacity supported by a hearty I/O (input/output) subsystem.
Several standardized I/O buses are available to the system designer including: ISA (Industry Standard Architecture), EISA (Extended Industry Standard Architecture), PCI (Peripheral Component Interface), and VESA (Video Electronics Standards Association) local bus sometimes called VL-bus or VLB. Today's computers are typically designed with a PCI bus with either an ISA bus or EISA bus. Familiarity with the PCI Local Bus Specification, Production Version, Revision 2.1, dated Jun. 1, 1995, which is published by the PCI Special Interest Group of Hillsboro, Oreg., is assumed for the purposes of this application, and it is hereby incorporated by reference.
When an ISA or EISA bus is present standard I/O peripherals, such as a floppy disk, are connected to the ISA or EISA bus. This is particularly relevant since the floppy disk is a peripheral which uses direct memory access (DMA).
Direct memory access is a method by which a peripheral may access memory without processor intervention, provided the DMA transfer was previously initialized. DMA transfers are normally used to transfer blocks of data between an I/O device, such as the floppy disk controller, and memory. Direct memory access reduces the amount of processor interactions with memory, thereby freeing the processor for other processing tasks.
The legacy of the IBM (International Business Machines) AT class personal computer (PC) dictates that compatible computer systems include two DMA controllers on the ISA bus. These DMA controllers are functionally compatible with an 8237 DMA controller made by Intel and other companies. The DMA controllers conventionally reside in the personal computer at certain address ranges. Although more recently it is common to combine the functionality of the DMA controller with other functions traditionally found on the ISA bus into a single integrated circuit to conserve circuit board space, the DMA controller is still present at the compatible address ranges. A representative description of the DMA controller is found in the 8237 A High Performance Programmable DMA Controller datasheet published by Intel Corporation, and hereby incorporated by reference. Technical data regarding the implementation of DMA controllers in a PC can be found in technical literature such as the Compaq Deskpro 386 Personal Computer Technical Reference Guide, Volume I, chapter 2, hereby incorporated by reference. Familiarity with the DMA controller is assumed.
The DMA controller is a peripheral interface circuit for allowing peripheral devices to directly transfer data between main memory. It includes four independent channels and may be expanded to any number of channels by cascading additional controller chips. In the PC architecture, two DMA controllers are used. One DMA controller is used for byte transfers, and the second DMA controller is user for word (16-bit) transfers. All four channels (designated 0, 1,2 and 3) of the byte-wide DMA controller are dedicated to performing byte DMA operations. Of the four channels (designated 4,5,6 and 7) of the word-wide DMA controller, channels 5,6 and 7 are dedicated for word DMA operations. Channel 4 is used for cascading the two controllers together and, therefore, is not available for normal DMA. Because the byte-wide DMA controller is cascaded into the word-wide DMA controller, the byte-wide DMA controller is sometimes called the secondary DMA controller and the word-wide DMA controller is called the primary DMA controller.
The ISA and EISA buses include signals for performing DMA operations. A peripheral connected to the ISA bus may request a DMA operation by providing a DMA request signal (DREQ*, where * is the channel number) over the ISA bus to the DMA controller. In response to a DREQ signal, the DMA controller will provide a DMA acknowledge (DACK*) signal to the peripheral when the DMA controller has been granted the ISA bus and is ready to perform the operation. The DMA controller then accesses the peripheral to move data over the ISA bus and between the peripheral and memory. However, since the PCI bus or the VL-bus do not incorporate the ISA DMA signals, ISA DMA devices cannot be placed on these buses.
With the PCI bus becoming more popular because of its higher performance, it is desirable to connect many of the ISA peripherals directly to the PCI bus instead of the ISA bus. However, the incompatibility between the ISA DMA controller architecture and the PCI bus prevents the joining of these components.
In certain systems, such as portable computers, the limited space requirements allow only one expansion bus to be supported. If only the PCI bus is provided and the ISA bus is not, then ISA DMA capability is not directly supported. One method of supporting the ISA DMA operations is to include the DMA controllers in a single PCI device. However, all DMA devices must connect to this single device, so essentially the ISA bus must be present. Another alternative is to place the DMA controllers on the PCI bus. The special DMA signals can then be routed as sideband signals without interfering with PCI operations. However, with the advent of Plug and Play, any function that supports DMA should be programmable to more than one channel without the use of jumpers, and therefore, the relatively high number of sideband signals (fourteen DREQ* and DACK* signals) cause this solution to be unworkable, especially for portable applications. Familiarity with the Plug and Play Specification hereby incorporated by reference, available from Microsoft Corporation, is assumed for the purposes of this application.
Moreover, the DMA signals could be serialized to reduce pinouts, but then response time on the negative edge of the DREQ* signals might lead to late terminations. Therefore, this solution is not preferred.
The performance of the PCI bus is much greater than that of the ISA and EISA buses. Further, by not providing a PCI to ISA bridge chip costs can be reduced. As such, it is desirable to create a mechanism for incorporating ISA type DMA into devices that connect directly to the PCI bus or VL-bus so that a more flexible solution to ISA DMA can be provided for portable computers.